Modify your design so the specified source I/O pin drives only the specified I/O input buffer primitive.įile: C:/Echodyne/FPGA_Files/A_Current_Files/ADC_Card5_S8_Vector_LB/Q_SYS_ALL/Q_SYS_ALL/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv Line: 954 :altdq_dqs2_inst|obuf_os_0 drives out to destinations other than the specified I/O input buffer primitive. Source I/O pin ADC_Block:U1|q_sys_all:b2v_inst10|q_sys_all_DDR3_V RB:ddr3_vrb|q_sys_all_DDR3_VRB_p0
:uio_pads|q_sys_all_DDR3_VRB_p0_altdqdqs:dq_ddio.ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_ cyclonev :p0|q_sys_all_DDR3_VRB_p0_acv_hard_memphy:umemphy| q_sys_all_DDR3_VRB_p0_acv_hard_io_pads Does anyone know what this message means, and how I can fix it?Įrror (17044): Illegal connection on I/O input buffer primitive ADC_Block
I have a need to add the 32-bit memory to the mix. The other bank is 32-bits wide and uses a hard core. One bank is 64-bits wide, and uses a soft core. I have been working with this board for about 2 years. I am using the Altera Cyclone V GT development kit.
Quartus II 64-Bit Version 13.0.1 Build 232 SJ Web Edition
QUARTUS PRIME LITE 17 HOW TO
I'm having a problem when a try to compile some vhdl codes in Quartus, Someone here knows how to fix it?
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